The present invention generally relates to the field of semiconductor memories. More particularly, the present invention relates to a DRAM and a memory core utilizable in embedded memories including DRAMs (dynamic random access memories) and logical circuits.
The level of integration of memories, particularly the level of DRAM integration, has been improved increasingly year by year. In order to avoid a reduction of the serviceable time of memories, a longer refresh cycle period is required. The level of real performance values required for data retention times becomes higher. It seems hard for process devices to meet such requirements.
Referring now to FIG. 23, the value of real performance of the memory data retention time will be described.
FIG. 23 outlines a conventional DRAM. Cs is a storage capacitor in a DRAM memory cell. WL1 and WL2 are word lines. bit is a bit line and xbit is a bit line in complementary relationship with the bit line bit. Vpre is a bit line precharge voltage. Ppre is a precharge control line. SA is a sense amplifier.
The operation of the DRAM is briefly explained. The precharge control line Ppre first enters the high level state and the bit lines bit and xbit are set at the precharge level Vpre. Subsequently, the precharge control line Ppre enters the low level state. This is followed by an increase in the potential of the word line WL1 and a micropotential is produced by a signal charge, stored in the memory cell storage capacitor Cs, in the bit line bit. This micropotential produced is subjected to amplification processing in the sense amplifier SA.
If a potential just before the word line WL1 undergoes an increase in potential, stored in the memory cell storage capacitor Cs, is Vcs, then a conservation of charge before and after a cell transistor conducts can be written by:
Cs(Vcsxe2x88x92Vplate)+Vpre*CB=Cs(Vrxe2x80x2xe2x88x92Vplate)+Vrxe2x80x2*CB 
where Vplate is the cell plate potential, CB is the capacitance of the bit lines bit and xbit, and Vrxe2x80x2 is the bit line potential determined after an electric charge is read out from the memory cell.
From this equation, a microvoltage Delta xe2x88x92V to be amplified in the sense amplifier SA is expressed by:
Delta xe2x88x92V=Vrxe2x80x2xe2x88x92Vpre=a*(Vcsxe2x88x92Vpre) 
a=Cs/(Cs+CB) 
Only when the microvoltage Delta xe2x88x92V exceeds the sensitivity limit of the sense amplifier SA (+xe2x88x92Vsa), data are read out correctly. For example, if a xe2x80x9c1xe2x80x9d is written and is then read out, this produces a voltage expressed by:
Delta xe2x88x92V=a*(Vddxe2x88x92Vpre)=0.2*(3.3xe2x88x921.65)=330 mV 
where Vdd is the supply voltage. On the other hand, if a xe2x80x9c0xe2x80x9d is written and is then read out, this produces a potential that may be expressed by:
Delta xe2x88x92V=a*(0xe2x88x92Vpre)=0.2*(0xe2x88x921.65)=xe2x88x92330 mV 
Here, a=0.2, Vdd=3.3 V, and Vpre=Vdd/2.
Usually, the sense amplifier""s sensitivity limit Vsa is about 50 mV. The DRAM operates normally without problems.
Next, consider a case in which there occurs a leakage current from the memory cell storage capacitor Cs therefore producing a difference between a voltage written to Cs and a voltage read out from Cs. For instance, suppose here a case of writing a xe2x80x9c1xe2x80x9d, wherein a malfunction occurs at the time when the level of voltage reduces down to Vcs1L. It follows from a*(Vcs1Lxe2x88x92Vpre)=Vsa that 0.2*(Vcs1Lxe2x88x921.65)=0.05. This shows that the malfunction starts occurring when Vcs1L=1.9 V. A length of time up to the time such a limit is reached is a real performance value of the data retention time. This relationship is illustrated by reference to FIG. 24.
Accordingly, an object of the present invention is to provide a longer data retention time for the realization of a longer refresh cycle period. Another object of the present invention is to prevent poor yields caused by short data retention times to achieve a reduction of the entire process cost.
In order to accomplish these objects, the reference potential in sense amplifiers is decreased corresponding to the decrease of voltage due to leakage current in memory cells.
The present invention provides a semiconductor memory comprising:
an information memory cell of a capacitor and a transistor for performing operations of reading out information;
a word line for accessing the memory cell; and
a reference memory cell other than the information memory cell, the reference memory cell being coupled to the word line or to a word line having the same address as the word line;
wherein the reference memory cell stores information for use by a sense amplifier, the information being reference information equivalent to a reference potential to the reading of information from the information memory cell.
In the semiconductor memory it is preferred that the number of information memory cells is greater than the number of reference memory cells by one or more.
In one embodiment the number of reference memory cells is two, these two reference memory cells storing information of 1 and information of 0, respectively, and that the semiconductor memory further comprises a reference potential generation circuit capable of generating, based on the information stored in the two reference memory cells, a reference potential.
In another embodiment three or more information memory cells and three or more reference memory cells each store multi-bit information are utilized and the semiconductor memory further comprises a reference potential generation circuit capable of generating, based on the multi-bit information stored in the reference memory cells, a reference potential.
In a further embodiment a first memory cell group composed of information memory cells is divided into two approximately equal subgroups and a second memory cell group composed of reference memory cells for storing reference information is placed between the subgroups.
In accordance with the present invention, the reference potential stored in a memory cell different from an information memory cell is designed to fall corresponding to a decrease in potential of the information memory cell due to a leakage of the signal charge, whereby a length of time, for the difference between the information potential and the reference potential to reach a sense limit, can be decreased. As a result, a longer data retention time is obtained.